The Electrical Engineering and Computer Science Department at the University of Tennessee is a participant in Cadence Design Systems' university program which is designed to facilitate the use of Cadence Design Systems tools by undergraduate and graduate students in engineering courses and in academic research. This page contains only information about Cadence products currently in use by the academic programs of the University.
Undergraduate students in this course use the Custom Integrated Circuits Bundle to develop circuit design methodologies, including simulation and physical layout of CMOS digital circuit structures.
Graduate students in this course use the Custom Integrated Circuits bundle to aid in VLSI design, circuit capture, circuit simulation, and layout of custom integrated circuits.
Students in this graduate course use the Custom Integrated Circuits Bundle to enter designs as a schematic using Composer and simulate using Verilog-XL and/or Spectre. They then use Virtuoso to perform the layout, followed by DRC and extraction for post-layout simulation. The resulting designs are submitted to MOSIS for fabrication and subsequent testing.
Information is provided "as is" without warranty of any kind. No statement is made and no attempt has been made to examine the information, either with respect to operability, origin, authorship, or otherwise. Please use this information at your own risk. We recommend using it on a copy of your data to be sure you understand what it does under your conditions.
Cadence is a registered trademark of Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134.
Knoxville, Tennessee 37996 | 865-974-1000
The flagship campus of the University of Tennessee System