Monday, Room 200-D, Data Converters

10:20-11:50 Data Converters Tutorial–Part 1

11:50-13:20 Lunch

13:20-14:50 Data Converters Tutorial–Part 2

Tuesday, Lecture Hall, Delay Testing

10:20-11:50 Delay Testing Tutorial–Part 1

11:50-13:20 Lunch

13:20-14:50 Delay Testing Tutorial–Part 2

Wednesday, Lecture Hall, Nano-embedded System Design

This tutorial has been cancelled.

Monday, Room 200-D, Data Converters

“Design & Test of Low-Power/High-Speed Data Converters”

Integrated circuits with analog and digital functions have become more important than ever in complex applications, like wireless communications, video analog-front-end, and digital modem (xDSL: Digital Subscriber Line). Analog-to-digital (A/D) converters and digital-to-analog (D/A) converters are needed in these Mixed-Signal VLSI circuits to join the analog environment to the Digital Signal Processing (DSP) unit. The usage of data converters has become increasingly prevalent as DSP continues to gain ground over analog signal processing. The high-speed and high-resolution A/D converters are required in numerous applications. This tutorial focuses on the design and test of different types of converter architectures. Among the choices in A/D architectures are pipeline, folding and interpolation, and sigma-delta converters.

Digital-to-analog architectures include current-mode and sigma-delta converters.
Test of data converters requires lots of expertise in digital signal processing. However, the design of high performance data converters needs VLSI circuit design techniques. The test procedure should be cost effective and to be carried out in reasonable time. The test setup and post processing of collected data will be described. Some mixed signal Design-for-Test (DfT) architectures like Built-In-Self -Test (BIST) are included.

This tutorial will cover the following topics:

1. General Applications of A/D and D/A Converters
2. Performance Measures of High Speed and High Resolution Data Converters
3. Different Analog-to-Digital Architectures
3.1. Pipelined
3.2. Folding and Interpolation
3.3. Sigma-Delta
4. Different Digital-to-Analog Architectures
4.1. Current-Steering Architectures
4.2. Sigma-Delta D/A
5. DSP based Test of Data Converters
5.1. Static Linearity Tests (Ramp Test Method, Servo-Loop Test Method)
5.2. Dynamic Linearity Tests (Histogram-, FFT-, and Pulse-Testing, Curve Fitting)
6. Design for Test (DfT) of A/D Converters
6.1. Advantages
6.2. Built-In-Self-Test (BIST)
6.3. Oscillation BIST Technique
7. Conclusions

Instructor:

Dr. Mansour Keramat is currently CEO and co-founder of Alvand Technologies, Inc. (Santa Clara, CA) focusing on design of ultra-low power/low cost data-converters for wireless and wired communications. He received the B.S. degree in electrical engineering in 1989 and the M.S. degree in electronics in 1992 both from Sharif University of Technology, Tehran. He also received the second M.S. degree in signal processing and integrated sensors in 1994 and Ph.D. degree in statistical VLSI circuit design in 1998 both from the University of Paris-Sud (XI) and Ecole Superieure d’Electricite (SUPELEC). In 1992, he joined the Department of Electrical Engineering of Sharif University of Technology as a lecturer. He was a Visiting Assistant Professor in the Department of Electrical Engineering, Texas A&M University from February 1998 to August 1999 and an Assistant Professor in the Electrical and Computer Engineering Department at University of Connecticut from 1999 to 2001.

For additional information, visit Dr. Keramat's website

Tuesday, Lecture Hall, Delay Testing

“High-Quality Delay Tests for Nanometer Technology Designs: Challenges and Solutions”

To meet the market demand, the next generation of technology appears with an ever increasing speed and performance driving the manufacturing process to its limit. The demand for low power consumption in battery operated devices, higher frequency and higher functional density has introduced new challenges to design and test engineers. Reducing the power supply voltage will lower the total power consumption but increases the circuit sensitivity to noise since the voltage threshold is not scaling proportionally. Higher frequency and functional density will increase the power consumption producing more heat in the design and result in larger power supply noise. Integration of several cores for higher performance and throughput leads to longer interconnects thereby increasing coupling capacitance. As a result, performance verification has become one of the most challenging tasks for nanometer technology designs.

Delay test has gained popularity in industry over the past several years as a reliable method for post-silicon performance verification. Industry began using functional patterns first, but as the design size became larger, the high cost of generation as such patterns usually are generated manually, and low fault coverage forced functional at-speed test as a supplement to structural test in many seminconductor companies' design-for-test (DfT) flow. Instead, scan-based delay fault test methods gained attention primarily due to the very high fault coverage and their simple procedure to generate patterns. Scan-based path delay fault test and transition delay fault test, together, can provide a high quality test. However, there are new challenges surfacing in nanometer technologies mainly due to the difference in the operating conditions during test mode and normal mode. For instance, power during test mode is 2-3X higher than normal mode resulting in higher power supply noise which in turn impacts circuit performance. Other important issues include implementation of scan-based methods using low-cost testers, improving fault coverage and reducing pattern count. Increasing populations of small delay defects also need to be considered as they present quality and reliability issues.

In general, the goal of this tutorial is to provide the knowledge of delay models and tools for implementing practice-oriented delay test methodologies. This tutorial will cover the following topics:

1. Basics of delay testing, path and transition delay fault models.
2. Delay testing methods and ATPG
2a. Functional test
2b. Launch-off-shift
2c. Launch-off-capture
2d. Enhanced scan
3. Delay testing challenges and solutions in nanometer technology designs
3a. Process variations
3b. Small delay defects
3c. Test power and supply voltage noise
3d. Crosstalk
3e. Utilizing low-cost testers

Instructor:

Dr. Mohammad Tehranipoor is currently an Assistant Professor of Electrical & Computer Engineering at the University of Connecticut. He was also on the faculty of the CSEE department at the University of Maryland Baltimore (UMBC) from 2004 to 2006. His currenct research projects include: computer-aided design and test for CMOS VLSI designs and emerging nanoscale devices, design-for-testability, at-speed test, secure design and IC trust.

For additional information, visit Dr. Tehranipoor's website