Monday, August 11: 8:30 a.m. - 10:00 a.m.

The last several years have seen an increasing demand for portable applications, and as a result, many applications are power constrained, resulting in an ever increasing demand for increased computational resources in a constant power environment. One approach would be to consider using analog techniques, which shows order of magnitude improved power efficiencies, but lacks the programmability, configurability, and technical infrastructure that we see with typical digital techniques. Recent advances in analog signal processing, neuromorphic engineering, and programmable / configurable analog approaches seem to have bridged these gaps, and as a result could launch an exponential growth in analog computation that we saw in in digital IC design over 30 years ago.

We will start with a short history on how digital circuits progressed from a circuit centric technology to a very high-level system technology. We will notice that a programmable digital technology overtook a relatively fixed analog technology. We will discuss how the analog circuit and signal processing techniques have progressed, including discussing our research at Georgia Tech on programmable analog circuits, programmable system design, and configurable systems. We will then present possible roadmaps of analog signal processing technology going forward, as well as the upcoming challenges for these approaches to reach the level of design complexity we currently expect for digital computation.

Paul Hasler is an Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. Dr. Hasler received his M.S. and B.S.E. in Electrical Engineering from Arizona State University in 1991, and received his Ph.D. from the California Institute of Technology in Computation and Neural Systems in 1997. His current research interests include low power electronics, mixed-signal system ICs, floating-gate MOS transistors, adaptive information processing systems, “smart” interfaces for sensors, cooperative analog-digital signal processing, device physics related to submicron devices or floating-gate devices, and analog VLSI models of on-chip learning and sensory processing in neurobiology. Dr. Hasler received the NSF CAREER Award in 2001, and the ONR YIP award in 2002. Dr. Hasler received the Paul Raphorst Best Paper Award, IEEE Electron Devices Society, 1997, IEEE CICC best paper award, 2005, Best student paper award, IEEE Ultrasound Symposium, 2006, and IEEE ISCAS Sensors best paper award, 2005. Dr. Hasler is a Senior Member of the IEEE.

Tuesday, August 12: 8:30 a.m. - 10:00 a.m.

Secure communications among mobile components, like wireless sensors and RFID tags, emerge as a fundamental branch of network security, necessitating message confidentiality, integrity and authentication. That is, protecting the content of transmitted information, assuring that it was not altered during transmission, and proving that it was sent by an approved identified source. Hardware implementation of approved and strong security measures in mobile components is a scientific and engineering challenge, reflecting needs for novel solutions that also open avenues for far reaching applications beyond the specific issue at hand. The talk will present a novel approach to hardware minimization, serving message security while relying on approved security level. It will further be shown that memory security is not merely a physical problem, apparently independent of the served applications. This observation can be made general and deserves a thorough study in itself. To complement the above, recently announced logic gates fabrication techniques will be reviewed, along with their relation to the devised approach, as well as their potential contribution to general security applications.

Benjamin Arazi is a Professor in the Department of Electrical and Computer Engineering at Ben Gurion University, Israel. His current research interests include hardware and software aspects of secure communications in constrained environments, memory security, secured distributed computing, process control security, food safety, healthcare security, and security aspects of unified communications and virtual worlds. Dr. Arazi developed an algorithm, named after him, for performing a fundamental cryptographic operation in a smartcard. Other work of his appears in Knuth's “The Art of Computer Programming”. Dr. Arazi was the CTO of two companies involved in microchip design for security applications. He is a PI and co-PI on several federal grants totaling over $800K in the past 3 years. Dr. Arazi is an IEEE Distinguished Lecturer and an author of an MIT Press book on coding theory.

Wednesday, August 13: 8:30 a.m. - 10:00 a.m.

A decade ago, physical synthesis emerged as a design aid to address the problem of optimization after cell placement caused by increasingly high wire delays. Early physical synthesis tools were fairly simplistic scripts wrapped around traditional placement and logic synthesis optimizations. Advances and technology have put increasing pressure on physical synthesis tools not only to perform timing takedown with increasingly aggressive frequences but also to manage many additional design constraints like power management, routability, and variability. Trying to solve all aspects of physical implementation simultaneously creates massive complexity for both the tool and the designer.

This talk overviews the basics of physical synthesis, from placement to buffering to gate sizings and explains fundamentally how a physical synthesis flow weaves together its components to perform timing closure. It explains how the complexity of physical synthesis and corresponding designs have mushroomed to create design problems that are not just bad, but sometimes downright ugly.

Charles (Chuck) Alpert received two undergraduate degrees from Stanford University in 1991 and his doctorate from UCLA in 1996 in Computer Science. Upon graduation, Chuck joined IBM's Austin Research Laboratory where he remains still. He currently manages the Design Productivity Group, whose mission is to architect design automation tools and methodologies to improve designer productivity and reduce design cost. Chuck is the proud husband to his wife Cheryl and their three girls Candice, Ciara, and Charlie.

Chuck has published over 100 conference and journal papers and has thrice received the Best Paper Award from the ACM/IEEE Design Automation Conference. He has been active in the academic community, serving as chair for the Tau Workshop on Timing Issues and the International Symposium on Physical Design. He also serves as an associate editor of IEEE Transactions on Computer-Aided Design. For his work in mentoring, he received the Mahboob Khan Mentor Award in 2001 and 2007. He was also named IEEE Fellow in 2005.